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1 for more information www.linear.com/ltc3110 typical a pplica t ion fea t ures descrip t ion 2a bidir ectional buck-boost dc/dc regulator and charger/balancer the lt c ? 3110 is a 2a bidirectional buck-boost dc/dc regulator with capacitor charger and balancer. its wide 0.1v to 5.5v capacitor/ battery voltage and 1.8v to 5.25v system backup voltage ranges make it well suited to a wide variety of backup applications using supercapacitors or batteries. a proprietary low noise switching algorithm optimizes efficiency with capacitor/ battery voltages that are above, below or equal to the system output voltage. the ltc3110 can autonomously transition from charge to backup mode or switch modes based on an external command. pin-selectable burst mode operation reduces standby current and improves light-load efficiency, which combined with a 1 a shutdown current make the ltc3110 ideally suited for backup applications. additional features include voltage supervisors for direction control and end of charge, and a general purpose comparator with open-col - lector output for interfacing with a c. the ltc3110 is avail - able in thermally enhanced, low profile 24-lead tssop and 4mm 4mm qfn packages. a pplica t ions n v cap operating range: 0.1v to 5.5v n v sys operating range: 1.71v to 5.25v n automatic switchover from charge to backup mode n programmable 2% accurate charge input current limit from 125ma to 2a n 1% backup v oltage accuracy n automatic backup capacitor balancing n fixed 1.2mhz switching frequency n burst mode ? operation: 40a quiescent current n built-in programmable multipurpose comparator with open-collector output n open-collector outputs to indicate direction of operation and end of charge n thermally enhanced tssop-24 and 4mm??4mm qfn-24 packages n supercapacitor backup converter and charger n battery backup converter and charger n servers, raid systems n rf systems with battery/capacitor backup l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. backup mode efficiency 2.2h 0.1v up to 5.5v sw2 ltc3110 sv sys v sys 51.1 47f 220nf 12v bus 1f 0.1f 10f 10f 1960k 13.7k 1.50k 976k 221k 1000k 3110 ta01a 1000k 1.2v 1.8v 2.5v v sys 3.25v 2a c end of chrg caplow 12v bus supervisor 523k sw1v cap fbv cap cmpin mode run pgnd v mid r sen prog fb chrg capok cmpout dir sgnd system dc/dc regulators main step-down dc/dc fb i charge i backup v cap (v) efficiency (%) power loss (w) 0.8 0.6 0.4 0.2 0 3110 ta01b 1.2 1.0 90 85 80 75 70 100 95 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 v sys = 3.25v i sys = 0.5a ltc 3110 3110f
2 for more information www.linear.com/ltc3110 a bsolu t e maxi m u m r a t ings v cap , v sys , sv sys , v mode , v cmpin , v dir , v run , v capok , v cmpout , v chrg ...... C0.3 v to 6v r sen dc current ..................................................... 1.6 a o perating junction temperature range ( notes 2, 3) ............................................ C 40 c to 125 c (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3110efe#pbf ltc3110efe#trpbf ltc3110fe 24-lead plastic tssop C40c to 125c ltc3110ife#pbf ltc3110ife#trpbf ltc3110fe 24-lead plastic tssop C40c to 125c ltc3110euf#pbf ltc3110euf#trpbf 3110 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3110iuf#pbf ltc3110iuf#trpbf 3110 24-lead (4mm 4mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion storage temperature range .................. C 65 c to 150 c lead soldering temperature ( soldering , 10 sec ) ts sop .............................................................. 30 0 c reflow peak body temperature (30 sec max ) qfn ................................................................... 26 0 c 1 2 3 4 5 6 7 8 9 10 11 12 top view fe package 24-lead plastic tssop 24 23 22 21 20 19 18 17 16 15 14 13 capok cmpout mode cmpin fbvcap sgnd dir run fb prog chrg sv sys v mid v cap v cap sw1 sw1 pgnd pgnd sw2 sw2 v sys r sen v sys 25 pgnd t jmax = 150c, ja = 33c/w, jc = 5c/w, 4 layer board exposed pad ( pin 25) is pgnd, must be soldered to pcb 24 23 22 21 20 19 7 8 9 top view 25 pgnd uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 cmpin fbvcap sgnd dir run fb sw1 sw1 pgnd pgnd sw2 sw2 mode cmpout capok v mid v cap v cap prog chrg sv sys v sys r sen v sys t jmax = 150c, ja = 37c/w, jc = 4.5c/w, 4 layer board exposed pad ( pin 25) is pgnd, must be soldered to pcb ltc 3110 3110f
3 for more information www.linear.com/ltc3110 parameter conditions min typ max units v cap no-load operating range in backup operation v sys 1.8v 0.1 5.5 v v cap start-up v sys < undervoltage lockout threshold l 1.8 v v sys operating range in charge operation v dir = v sys l 1.8 5.25 v undervoltage lockout threshold v sys ramping down, v cap = 0v v sys ramping up, v cap = 0v l 1.55 1.71 v v v cap ramping down, v sys = 0v, v run = v cap v cap ramping up, v sys = 0v, v run = v cap l 1.55 1.71 v v fb feedback v oltage 0c < t j < 85c (note 5) C40c < t j < 150c l 0.592 0.589 0.6 0.6 0.608 0.611 v v fb feedback pin input current 0.1 50 na fbv cap end-of-charge threshold rising dir = v sys l 1.095 1.117 v fbv cap end-of-charge threshold falling dir = v sys l 1.040 1.061 v fbv cap input current v fbvcap = 1.1v 0.1 50 na fbv cap overcharge threshold rising 1.125 1.150 1.175 v fbv cap overcharge hysteresis 35 mv quiescent current, burst mode operation (i vcap + i vsys + i svsys ) v mode = 0v 40 a quiescent current, end of charge ( i vcap + i vsys + i svsys ) v dir = v sys 40 a quiescent current, shutdown (i vcap ) v run = 0v, v sys = sv sys = 0v 0.05 1 a peak current limit in backup operation (note 4) 5 6 7 a dc current limit in backup operation (note 4) l 3.5 4.5 a peak current limit in charge operation ( note 4) 5 6 7 a reverse current limit in backup operation (note 4) 1 1.2 2 a switch leakage switch b, c: v cap ?=?v sw1 ?=?5.5v, v sys ?=?v sw2 ?=?5.25v, 0.1 a switch a, d: v cap = 5.5v, v sys = 5.25v v sw1 = v sw2 = 0v 0.1 a switch on-resistance switch a (note 6) switch b (note 6) switch c (note 6) switch d including sense resistor (note 6) 64 49 49 86 m m m m oscillator frequency v cap = 0.2v v sys = 0.2v l 900 1200 300 300 1500 khz khz khz soft start-up t ime in backup mode from v run rising to v fb = 90% 0.8 1.3 1.8 ms maximum duty cycle in boost mode v cap = 0.2v l 91 93 98 96 % % minimum duty cycle in buck mode l 0 % mode input logic threshold enable burst mode operation enable pwm mode operation 1 0.3 v v mode input pull-down resistor 6 m dir threshold rising l 1.073 1.095 1.117 v dir threshold falling l 1.024 1.045 1.066 v dir hysteresis l 30 50 70 mv dir input current v dir = 5.5v 0.1 50 na e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cap = 3.3v, v sys = 3.3v, v dir = v sgnd , v mode = v run = v sys = sv sys unless otherwise noted. ltc 3110 3110f
4 for more information www.linear.com/ltc3110 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cap = 3.3v, v sys = 3.3v, v dir = v sgnd , v mode = v run = v sys = sv sys unless otherwise noted. e lec t rical c harac t eris t ics parameter conditions min typ max units cmpin threshold rising 0.638 0.65 0.662 v cmpin threshold falling l 0.575 0.59 0.605 v cmpin input current v cmpin = 5.5v 0.1 50 na prog voltage v fbvcap = 1v, dir = v sys 0.6 v prog current gain dir = v sys 200 a/a i vsys input current limit r prog = 24.3k (notes 7, 8), dir = v sys r prog = 24.3k (notes 7, 8, 9), dir = v sys r prog = 12.1k (notes 7, 8), dir = v sys r prog = 12.1k (notes 7, 8, 9), dir = v sys r prog = 6.04k (notes 7, 8), dir = v sys r prog = 6.04k (notes 7, 8, 9), dir = v sys r prog = 3.01k (notes 7, 8), dir = v sys r prog = 3.01k (notes 7, 8, 9), dir = v sys r prog = 1.5k (notes 7, 8), dir = v sys r prog = 1.5k (notes 7, 8, 9), dir = v sys l l l l l 119 115 241 234 487 473 977 948 1960 1900 123 123 248 248 497 497 997 997 2000 2000 128 131 255 262 507 521 1017 1046 2040 2100 ma ma ma ma ma ma ma ma ma ma v mid to v cap voltage ratio v mid = open load, v cap = 5v 0.492 0.5 0.508 v mid balancing current v cap = 5v, v mid = 5v v cap = 5v, v mid = 0v l l 150 300 C300 C150 ma ma v mid current in shutdown v run = 0v 0.1 1 a v mid suspend charging threshold v mid rising, v cap = 5v v mid falling, v cap = 5v 2.38 2.6 2.4 2.62 v v chrg , capok, cmpout open-drain output voltage i = 10ma l 0.1 0.3 v run input logic threshold l 0.3 1 v run pull-down resistor 6 m note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3110 is tested under pulsed load conditions such that t j ~ t a . the ltc3110e is guaranteed to meet performance specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3110i is guaranteed to meet specifications over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. note 3: this ic includes overtemperature protection that is intended to protect the device during momentar y overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: current measurements are performed when the ltc3110 is not switching. the current limit values measured in operation will be somewhat higher due to the propagation delay of the comparators. note 5: guaranteed by design characterization and correlation with statistical process controls. note 6: guaranteed by design, correlation and bench measurements. note 7: current measurements are made when the output is not switching. note 8: accuracy of this specification is directly related to the accuracy of the resistor used to program the parameter. note 9: the input current limit reduces at junction temperatures above 130c (typical). see thermal foldback of charge current in the operation section. ltc 3110 3110f
5 for more information www.linear.com/ltc3110 typical p er f or m ance c harac t eris t ics r ds(on) of swa static maximum load current in pwm mode efficiency vs v cap voltage r ds(on) of swd dynamic including sense resistor maximum load current in burst mode operation burst mode efficiency r ds(on) of swd static including sense resistor r ds(on) of swa dynamic charge efficiency t a = 25c unless otherwise noted v cap (v) 0 0 i vsys (a) 1 2 3 4 5 1 2 3 4 3110 g04 5 5.5 pulsed load t = 1s 40% duty cycle u_v sys = 1.8v u_v sys = 3.3v u_v sys = 5.25v v cap (v) 0 0 i vsys (ma) 150 250 350 450 50 100 200 300 400 1 2 3 4 3110 g05 5 5.5 u_v sys = 1.8v u_v sys = 3.3v u_v sys = 5.25v v cap (v) 1.5 r ds(on) (m) 95 105 115 5.5 3110 g06 85 75 65 45 2.5 3.5 4.5 2 3 4 5 55 135 125 t j = 155c t j = 130c t j = 85c t j = 25c t j = 0c t j = ?45c v cap > ~75% ? v sys v cap (v) 0 r ds(on) (m) 65 70 75 4.54 3110 g07 60 55 45 1 2 3 0.5 5 1.5 2.5 3.5 50 85 80 t j = 155c t j = 125c t j = ?45c t j = 85c t j = 25c t j = 0c v cap < ~75% ? v sys v sys (v) 1.5 r ds(on) (m) 120 150 160 5.5 3110 g08 110 100 60 2.5 3.5 4.5 2 3 4 5 80 180 170 140 130 90 70 t j = 155c t j = 130c t j = 85c t j = 25c t j = 0c t j = ?45c v sys > ~75% ? v cap v sys (v) 1.5 60 r ds(on) (m) 65 75 80 85 3.5 105 3110 g09 70 2.5 2 4 3 4.5 90 95 100 t j = 155c t j = 125c t j = ?45c t j = 85c t j = 25c t j = 0c v sys < ~75% ? v cap v cap (v) 0.5 65 efficiency (%) 80 70 85 75 90 100 95 1.5 2.5 3.5 4.5 3110 g01 5.5 v sys = 3.25v pwm mode i sys = 0.2a i sys = 0.5a i sys = 1a i sys = 2a 0.001 0.01 0.1 i sys (a) 70 75 80 85 90 efficiency (%) v cap = 5v, v sys = 3.3v v cap = 2.5v, v sys = 1.8v 3110 g02 0.5 1.5 2.5 3.5 4.5 5.5 v cap (v) 0 0.5 1.0 1.5 2.0 2.5 efficiency (%) 50 60 70 80 90 100 power loss (w) v sys = 3.3v r prog = 3.01k 3110 g03 ltc 3110 3110f
6 for more information www.linear.com/ltc3110 feedback voltage vs v cap feedback voltage vs temperature v sys load regulation switching frequency vs v cap switching frequency vs v sys switching frequency vs temperature r ds(on) of swb r ds(on) of swc switch leakage vs temperature v cap (v) 200 switching frequency (khz) 600 1000 1400 400 800 1200 1 2 3 4 3110 g16 5.5 0.50 1.5 2.5 3.5 4.5 5 v sys = 3.3v v sys = 1.8v frequency foldback at low v cap v sys (v) 200 switching frequency (khz) 600 1000 1400 400 800 1200 1 2 3 4 3110 g17 5.5 0.50 1.5 2.5 3.5 4.5 5 v cap = 3.3v v cap = 1.8v frequency foldback at low v sys typical p er f or m ance c harac t eris t ics t a = 25c unless otherwise noted v cap (v) 1.5 r ds(on) (m) 80 90 100 105 95 85 75 3.5 4 5 60 70 40 50 55 65 35 45 30 2 2.5 3 4.5 5.5 6 3110 g10 t j = 155c t j = 125c t j = 85c t j = 25c t j = 0c t j = ?40c v sys (v) 1.5 r ds(on) (m) 80 90 100 105 95 85 75 3.5 4 5 60 70 40 50 55 65 35 45 30 2 2.5 3 4.5 5.5 6 3110 g11 t j = 155c t j = 125c t j = 85c t j = 25c t j = 0c t j = ?40c t j (c) ?45 switch leakage (a) 2.0 3.0 155 3110 g12 1.0 0 5 55 105 ?20 30 80 130 4.0 1.5 2.5 0.5 3.5 switch b, c switch a, d v cap (v) 0 ?1.0 v fb change from v cap = 2.4v (%) 0.5 0 0.5 1.0 1 2 3 4 3110 g13 5 i load = 1ma burst mode operation pwm mode t j (c) ?45 v fb change from 25c (%) 0 0.5 115 3110 g14 ?0.5 ?1.0 ?5 35 75 155 pwm mode 1.0 i load = 1ma burst mode operation i load (a) 0 ?1.0 voltage change (%) ?0.5 0 0.5 1.0 0.5 1.0 1.5 2.0 3110 g15 2.5 3.0 burst mode operation pwm mode t j (c) ?45 change from 25c (%) 0 0.5 155 3110 g18 ?0.5 ?1.0 5 55 105 1.0 ltc 3110 3110f
7 for more information www.linear.com/ltc3110 v prog programming voltage vs temperature v prog programming voltage vs temperature v prog programming voltage vs v fbvcap v prog programming voltage vs v cap fbv cap comparator thresholds vs temperature v prog programming voltage vs v sys dir thresholds vs temperature cmpin threshold voltage vs temperature i vsys input current limit vs r prog typical p er f or m ance c harac t eris t ics t a = 25c unless otherwise noted t j (c) ?45 v prog (v) 0.4 0.5 0.6 105 130 30 55 80 3110 g19 0.3 0.2 ?20 5 155 0.1 0 0.7 thermal charge current foldback t j (c) ?45 ?1.0 v prog change from 25c (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 5 55 80 105 3110 g20 ?0.6 0.6 0.8 0.2 ?20 30 130 v fbvcap (v) 0 0 v prog (v) 0.1 0.3 0.4 0.5 0.8 1.0 1.2 1.4 0.7 3110 g21 0.2 0.2 0.4 0.6 0.6 end of charge charge current foldback at end of charge v cap (v) 0 ?0.5 change in v prog from v cap = 1.8v (%) ?0.3 ?0.1 0.1 1 2 3 4 3110 g22 5 0.3 0.5 r prog = 6.04k ?0.4 ?0.2 0 0.2 0.4 v sys (v) 1.7 ?0.5 change in v prog from v sys = 3.3v (%) ?0.3 ?0.1 0.1 2.6 3.5 4.4 3110 g23 0.3 0.5 ?0.4 ?0.2 0 0.2 0.4 5.3 r prog = 6.04k t j (c) ?45 chagne from 25c (%) 0 0.5 115 3110 g24 ?0.5 ?1.0 ?5 35 75 155 1.0 falling rising t j (c) ?45 v fbvcap change from 25c (%) 0.2 0.6 1.0 115 3110 g25 ?0.2 ?0.6 0 0.4 0.8 ?0.4 ?0.8 ?1.0 ?5 35 75 ?25 135 15 55 95 155 falling rising t j (c) ?45 change from 25c (%) 0 75 155 3110 g26 ?0.5 ?1.0 ?5 35 115 0.5 1.0 falling rising r prog (k) 0 2 4 i vsys (ma) 1000 1500 3110 g27 500 0 6 8 10 12 14 16 18 20 22 24 2000 750 1250 250 1750 ltc 3110 3110f
8 for more information www.linear.com/ltc3110 v mid load regulation v mid buffer current vs v cap v mid vs temperature input current limit aging backup soft-start backup time i vsys input current vs v cap prog current gain vs temperature i vcap charge current vs v cap typical p er f or m ance c harac t eris t ics t a = 25c unless otherwise noted v cap (v) 0 0 i vsys (a) 1 2.00 0.50 1.50 2.50 1.0 2.0 3.0 4.0 3110 g28 5.0 r prog = 1.50k r prog = 3.01k r prog = 6.04k r prog = 12.4k t j (c) ?45 change from 25c (%) 0 3110 g29 ?1.0 ?2.0 15 75 ?15 45 105 1.0 2.0 ?0.5 ?1.5 0.5 1.5 135 r prog = 6.04k r prog = 3.01k r prog = 1.50k v cap (v) 0 0 current (a) 2 1 3 5 4 1 2 3 4 3001 g30 5 r prog = 1.50k r prog = 3.01k r prog = 6.04k r prog = 12.4k i mid (a) ?0.3 ?1.0 voltage change (%) ?0.5 0 0.5 1.0 ?0.2 ?0.1 0 0.1 3110 g31 0.2 0.3 v cap = 2.5v v cap = 5v v cap (v) 0 i vmid (a) 0 3110 g32 ?200 ?400 2 4 1 3 5 200 400 v mid = v cap v mid = p gnd ?100 ?300 100 300 6 t j (c) ?45 voltage change (%) 0 0.5 115 3110 g33 ?0.5 ?1.0 ?5 35 75 155 1.0 v cap = 5.5v no load v cap = 2.6v time (year) 0 ?1.00 change from t = 0 year (%) ?0.50 0 0.50 1.00 5 10 15 20 3110 g34 25 30 accelerated load life test data scaled to tj = 105c, i vsys = 2a conditions run 5v/div v sys 1v/div 0v 0a 200s/div 3110 g35 i l 0.2a/div 2s/div i load = c1 = c2 = 2.4f 2a 1a 0.5a 0.25a v cap 2v/div 0a 0v v sys 2v/div 3110 g45 ltc 3110 3110f
9 for more information www.linear.com/ltc3110 load step 0a to 2a burst mode operation charge balancer operation c1 > c2 charge sleep to backup transient in autonomous application pwm mode operation charge balancer operation c1 < c2 backup to charge transient in autonomous application pwm mode operation in v cap overvoltage failure condition single capacitor backup typical p er f or m ance c harac t eris t ics t a = 25c unless otherwise noted i load 1a/div 0a v sys 200mv/div 100s/div 3110 g37 il 1a/div v sys 1v/div chrgb 5v/div 0v 200s/div 3110 g38 0a il 1a/div v sys 1v/div chrgb 5v/div 0v 200s/div backup charging 3110 g39 0a 10ms/div v sys 50mv/div il 0.5a/div 0a 3110 g40 500ns/div sw1 1v/div sw2 1v/div 0a il 0.2a/div 3110 g41 i sys = 100ma 500ns/div il 100ma/div 0a sw1 5v/div sw2 5v/div 3110 g42 fb vcap = 1.2v v dir = 0v 1s/div v cap v mid i sys 1v/div 0a 0v 2v/div 3110 g43 1s/div v cap v mid i sys 1a/div 0a 0v 2v/div 3110 g44 v cap 1v/div v sys 1v/div 0v 0v 500ms/div 3110 g36 i load = 300ma c1 = 1.2f ltc 3110 3110f
10 for more information www.linear.com/ltc3110 p in func t ions (fe/ufd) capok ( pin 1/pin 22): v cap voltage ok indicator output . the open-drain output is pulled low if the fbv cap voltage is lower than the fbv cap falling threshold. the output is released if fbv cap is higher than the rising threshold. cmpout (pin 2/pin 23): general purpose compara- tor output. the open-drain output is pulled low while the cmpin pin voltage is above the comparator rising threshold . the output is released when cmpin is below the falling threshold. mode ( pin 3/pin 24): burst/ pwm mode selection input. driving mode to a logic 1 state programs fixed frequency, low noise pwm operation . driving mode low programs burst mode operation . note that the mode pin has no effect when operating in charger mode. cmpin ( pin 4/ pin 1): general purpose comparator positive input with hysteresis. the voltage at cmpin is compared to an internal reference voltage. the pin can be driven digitally or configured as voltage supervisor with the help of an external resistor divider. if driven from a resistor divider or from a source with >200 impedance, connect a 0.1f capacitor between cmpin and gnd for best performance . the cmpin rising threshold is 0.65v and the falling threshold is 0.59v. fbv cap ( pin 5/pin 2): v cap end-of-charge voltage pro - gramming feedback divider input with hysteresis. the end-of-charge threshold can be adjusted from 1.1v to 5.5v. the fbv cap rising threshold is 1.095v and falling threshold is 1.061v. sgnd ( pin 6/pin 3): signal ground connection. a ground plane is highly recommended. sensitive analog compo - nents terminated at ground should connect to the sgnd pin with a kelvin connection , separated from the high current path in pgnd. dir ( pin 7/ pin 4): charge/ backup mode selector input with hysteresis. a voltage on dir above the rising threshold enables the ltc3110 charger mode. a voltage below the falling threshold enables the backup mode. the pin can be driven digitally, e.g., from a c. with the help of an external resistor divider the pin can be configured as volt - age supervisor input monitoring any system voltage . the dir rising threshold is 1.095v and the falling threshold is 1.045v. run (pin 8/pin 5): logic-controlled shutdown input. run 1.0v: normal operation run 0.3v: shutdown fb (pin 9/pin 6): v sys backup voltage feedback pin . connect resistor divider tap here. the v sys voltage can be adjusted from 1.8v to 5.25v. the feedback reference voltage is 0.6v. prog ( pin 10/pin 7): charger input current (i vsys ) programming resistor. a resistor from prog to sgnd programs the average current flowing in v sys when op - erating in charging mode. r prog = 3k ? ? a i vsys for 1.5k ? < r prog < 24.3k ? r prog can be increased to 48.7k if the charge current fold - back is avoided with fbv cap held down < 1v or grounded. ltc 3110 3110f
11 for more information www.linear.com/ltc3110 p in func t ions (fe/ufd) chrg (pin 11/pin 8): charge/backup mode indicator output. the open-drain output is pulled low while the regulator is in charge mode. the open-drain output is released while the regulator is in backup mode. sv sys ( pin 12/pin 9): signal supply voltage input for buck/ boost controller circuitry. pin must be shorted to v sys or supplied from v sys through a rc filter . see the applications information section for details. v sys ( pins 13, 15/ pins 10, 12): bidirectional power supply pin for system backup output voltage and charge cur - rent input voltage . a bypass capacitor must be connected between v sys and pgnd. refer to the typical applications schematics and the applications information section for capacitor selection details. r sen ( pin 14/pin 11): current sense resistor tap at junc- tion of internal sense resistor and switch d. pin r sen is internally shorted to pin v sys via low impedance . dc current in r sen must be limited to 1.6a. sw2 ( pins 16, 17/pin 13, 14): switch pin connected to internal switches c and d of the buck-boost regulator. connect one side of the buck-boost inductor to sw2. provide a short wide pcb trace from the inductor to sw2 to minimize voltage transients and noise. pgnd ( pins 18, 19, exposed pad pin 25/pins 15, 16, exposed pad pin 25): power ground connection. termi - nate all high current ground paths to pgnd. the exposed pad must be soldered to the pcb ground for rated thermal per formance. sw1 (pins 20, 21/pins 17, 18): switch pin connected to internal switches a and b of the buck-boost regulator. connect one side of the buck-boost inductor to sw1. provide a short wide pcb trace from the inductor to sw1 to minimize voltage transients and noise. v cap ( pins 22, 23/pins 19, 20): bidirectional power pin for connection to supercap backup capacitor (s) or backup battery(ies). when in charge mode a current flows out of pin v cap to charge the storage elements connected be - tween v cap and pgnd. when in backup mode the current is flowing into pin v cap and the stored energy is used to backup the load on v sys . v mid ( pin 24/pin 21): active voltage balancing power output. this pin should be tied to the junction of two series supercapacitors. if the output is not used , a compensation capacitor of 1nf must be connected between pins v mid and pgnd. ltc 3110 3110f
12 for more information www.linear.com/ltc3110 b lock diagra m + ? + ? + ? v ref(prog) v th(dir) buck-boost control charger input current sense v th(chrg) d a b c sw1 l1 1.5h sw2 + ? v ref(fb) en fb r5 high = charging low = backup charging/backup r chrg r6 chrg charger enable osc run r1 r2 v sys r capok end of charge high = forced pwm low = burst mode operation high = enable low = shutdown r3 r4 capok overcharge threshold enable backup r mode dir v sys prog v sys r prog v cap buf voltage balancing mode + ? end of charge threshold fbv cap v mid v cap 0.1v to 5.5v r sen c svsys 220nf r svsys 51.1 r sen sv sys v sys c sys 47f v sys 1.8v to 5.25v 2a + ? + ? + ? + ? + ? + ? en r run v cap undervoltage lockout v sys v refok en sgnd lockout threshold cmpout v th(cmp) run cmpin v ref and bias temp shutdown v sys r caplow caplow c cap 1f c1 10f c2 10f pgnd 3110 bd comp comp c cmpin 0.1f ltc 3110 3110f
13 for more information www.linear.com/ltc3110 o pera t ion introduction the ltc3110 is a monolithic buck-boost dc/dc regulator/ charger combination with pin-selectable operation modes to utilize a single ltc3110 device for charging (v dir = high) as well as for system backup (v dir = low). during charging a limit for the average current drawn from the system power source can be accurately programmed with an external resistor . an integrated , active , voltage balancing buffer at pin v mid prevents capacitor overvoltage condi - tions caused from capacitor mismatch while charging a stack of super capacitors. the buck-boost regulator utilizes a proprietar y switching algorithm which allows the system voltage, v sys , to be regulated above, below, or equal to the voltage on the storage element, v cap , without discontinuity in inductor current or large voltage ripple in the backup voltage v sys . with the dir pin direction control circuitry , the ltc3110 can instantly reverse the inductor current and change between charging and backup operation modes, react - ing quickly on a power failure condition by providing the backup voltage to the system (see figure 1). the ltc3110 has been optimized to reduce quiescent current in shutdown and standby for applications that are sensitive to quiescent current drawn from the system voltage, v sys , or the storage element, v cap . in charge operation the standby current is only 40a. in backup/ burst mode operation, the no-load standby current is only 40a. in shutdown the total supply current is reduced to less than 1a. figure 1. transition from charge C into backup operation figure 2. charge foldback and charge termination charging when powered from the system voltage, v sys , the buck- boost regulator is usually set to operate in charge mode (v dir = high), that is, a voltage source connected to v sys is the power input into the ltc3110 and the converter charges a backup storage element connected between the v cap and pgnd pins. when operating in charge mode, the ltc3110 s average current limit circuitry is active. with a resistor between the prog and sgnd pins, the maximum average current drawn from v sys can be programmed to accurately limit the current demand. active charge balancer while charging, the integrated linear charge balancing buf - fer regulates the mid-voltage, v mid , of a stack of capacitors to half of v cap thus equalizing out voltage mismatches of top and bottom capacitor, see figure 3. if the capacitor mismatch is exceeding the current capabilities of the charge balancer, charging is suspended until v mid comes back to half of v cap ( see charging waveforms in the typical performance characteristics section ). note, the suspend charge function is only active for v cap > 2.2v ?=? v th(chrg) with hysteresis. for v cap < 2v the charger operation is always continuous. v sys 1v/div i l 1a/div 0a 200s/div 3110 f01 chrg 5v/div i sys 1a/div 0a 2v/div 1second/div 3110 f02 v cap v mid ltc 3110 3110f
14 for more information www.linear.com/ltc3110 o pera t ion v cap buf voltage balancing window comparator v mid r c1 c2 r 3110 f03 1 = allow charging 0 = suspend charging + ? + ? ltc3110 figure 3. active charge balancer charge termination the final charge voltage at pin v cap is programmed with a resistor divider at fbv cap , see figure 10 in the application information section. if fbv cap exceeds typically 95% of its end of charge threshold, the prog reference voltage and with it the charge current level begins to fold back (see figure 2). before charge termination the charge current is eventually folded back to a level of typically 30% of the programmed value ( see charging waveforms in the typical performance characteristic section). when the programmed voltage level is reached, the controller will terminate charging and switch off into a low quiescent current state wherein the charge balancer at the v mid pin is disabled and the capok pin is released. the low current state is maintained until the voltage on v cap decays and the fbv cap falling threshold is crossed. after this, controller and charge balancer will resume operation with the capok pin pulled low until the regulation voltage is reached again. note the ic cannot prevent outside sources leaking current into the capacitors from overvoltaging them. backup operation in fixed frequency pwm mode with the mode pin held high while v dir = low, the ltc3110 operates in a fixed-frequency pulse-width modulation ( pwm ) mode using a voltage mode control loop. this mode of operation maximizes the v sys backup current that can be delivered by the converter, reduces v sys voltage ripple, and yields a low noise fixed-frequency switching spectrum. a proprietary switching algorithm provides seamless transitions between operating modes and eliminates discontinuities in the average inductor cur - rent, inductor current ripple, and loop transfer function throughout all regions of operation . these advantages result in increased efficiency, improved loop stability, and lower v sys voltage ripple in comparison to the traditional 4-switch buck-boost converter. figure 4 shows the topology of the ltc3110 power stage which is comprised of two p-channel mosfet switches and two n-channel mosfet switches and their associated gate drivers. in response to the error amplifier output, an internal pulse-width modulator generates the appropri - ate switch duty cycles to maintain regulation of the v sys voltage. when the v cap voltage is significantly greater than the v sys voltage, the buck-boost converter operates in buck mode. switch d turns on continuously and switch c remains off. switches a and b are pulse-width modulated to produce the required duty cycle to support the v sys regulation voltage. as the v cap voltage decreases, switch a remains on for a larger portion of the switching cycle. when the duty cycle reaches approximately 90 %, the switch pair ac begins turning on for a small fraction of the switching period . as the v sys voltage decreases further, the ac switch pair remains on for longer durations and the duration of the bd phase decreases proportionally. at this point, switch a remains on continuously while switch pair cd is pulse- width modulated to obtain the desired v sys voltage. at this point , the converter is operating solely in boost mode. figure 4. buck-boost switch topology a d l b sw2 ltc3110 3110 f04 sw1 v cap v sys c ltc 3110 3110f
15 for more information www.linear.com/ltc3110 o pera t ion backup in burst mode operation when mode is held low while v dir = low, the buck-boost converter operates in burst mode operation using a vari - able frequency switching algorithm that minimizes the no-load input quiescent current and improves efficiency at light load by reducing the amount of switching to the minimum level required to support the load . the v sys current capability in burst mode operation is substantially lower than in pwm mode and is intended to support light stand-by loads. curves showing the maximum burst mode load current as a function of the v cap and v sys voltage can be found in the typical performance characteristics section of this data sheet. if the converter load in burst mode operation exceeds the maximum burst mode current capability, v sys will lose regulation. each burst mode cycle is initiated when switches a and c turn on producing a linearly increasing current through the inductor. when the inductor current reaches the burst mode peak current limit, switches a and c are turned off and switches? b and d are turned on, discharging the energy stored in the inductor into the v sys capacitor and load. once the inductor current reaches zero, all switches are turned off and the cycle is complete. current pulses generated in this manner are repeated as often as necessary to maintain regulation of the v sys voltage. v cap peak and dc-current limits (backup mode) the ltc3110 has two current limit circuits that are de - signed to limit the peak inductor current to ensure that the switch currents remain within the capabilities of the ic during output short-cir cuit or overload conditions. first current limit: in pwm mode the v cap dc current limit operates by injecting a current into the feedback pin (fb). for this current limit feature being most effective, the thevenin resistance (r bot //r top ) from fb to ground should exceed 100k. on a hard v sys short, with burst mode operation or pwm mode selected , it is possible for the inductor cur - rent to increase substantially beyond the dc current limit threshold . in this case the peak current, second current limit, turns off the power switch until the start of the next switching cycle. reverse current limit (backup mode) in pwm mode operation the ltc3110 has the ability to actively conduct current away from v sys if it is necessary to maintain regulation. if v sys is held above the regula- tion voltage, it could result in large reverse currents. this situation can occur if v sys of the ltc3110 is held up by another supply. to prevent damage to the part in this condition, the ltc3110 has a reverse current comparator that monitors the current entering power switch d from the load. if this current exceeds 1.2a (typical), switch d is turned off for the remainder of the switching cycle . for a no-load current application, the inductor current ripple must be lower than double the minimum reverse current limit (1a ? 2 = 2a maximum inductor current ripple). see the inductor selection section for information about how to calculate the inductor current ripple. preventing v cap overcharge failure due to reverse dc current(backup mode) if during pwm backup operation (mode ? =? high and dir ?= ?low), an external power supply or any second dc/dc regulator wrongly drives v sys higher than the programmed back-up voltage level, the ltc3110 will reverse its v sys current and simultaneously create reverse current flow charging v cap . if the wrong v sys voltage level is kept for a longer period of time, fb vap may exceed the overcharge threshold and the ltc3110 stops reverse charging. charging through reverse dc current while v dir is low is not indicated at pin chrg, which remains high impedance. the overcharge condition is generally prevented in the application by setting the ltc3110 into charge operation, if v sys is driven from an external source. if the external source is supervised from the dir com - parator, the chrg output can drive the gate of a pmos and isolate the external sour ce in backup operation , see applications with pfet on pages 29, 20, 31. if v sys is supervised from the dir comparator , the ex - ternal source must be capable to deliver more than the maximum reverse current limit of the ltc3110 in backup direction, see autonomous application on page 36. only if the external supply is strong enough, charge operation can be initiated reliably. ltc 3110 3110f
16 for more information www.linear.com/ltc3110 o pera t ion fb vcap failure condition external component failures, e. g., open or shorted resis - tors or leakage currents at pin fbv cap , can cause v cap to charge up to a higher, undefined voltage. if v cap exceeds typically 5.95v, the ltc3110 suspends charging which protects the ltc3110 from substantially exceeding the absolute maximum ratings if fbv cap is shorted to ground. note supercapacitors and batteries often have a lower maximum voltage rating than 5.95v. in these cases the general purpose comparator can be configured to detect the overvoltage at v cap ( see the figure general purpose comparator as redundant v cap supervisor in the applica - tion information section). soft -start (backup mode) t o minimize v cap current transients on power-up , the ltc3110 incorporates an internal soft-start circuit. the soft-start is implemented by a linearly increasing ramp of the error amplifier reference voltage during the soft- start duration. during the soft-start period the regulator is always operating in pwm operation independent of the mode pin setting. in case the v sys voltage at start-up is already pre-charged above 80 % of the target value, the soft-start is skipped and the ltc3110 immediately enters the mode of operation that has been set with the mode pin. the soft-start period is reset by thermal shutdown and from undervoltage lockout events. error amplifier and internal compensation of v sys backup voltage regulation the buck-boost converter utilizes a voltage mode error amplifier with an internal compensation network. error amplifier and internal compensation of v sys average current limit regulation the buck-boost converter in charge mode (dir = high) utilizes an error amplifier with an internal compensation network to regulate the average current flowing into the v sys pin. the current limit is programmable with r prog . r sen current sense resistor tap r sen connects to the junction of fet d and the integrated sense resistor. the r sen pin can be left unconnected, otherwise a load current, i rsen , will simultaneously decrease the average charge current flowing out of the v cap pin. note: a fast voltage step at v sys in the presence of a large r sen capaci- tor causes a large inrush current through the internal r sen resistor, e. g., closure of a mechanical power connection supplying v sys . in these cases, the value of the capacitor between r sen and ground is limited to a maximum of 10 f. v capok end-of-charge indicator and fbv cap comparator the ltc3110 includes an open-drain comparator output pin, v capok , which is used to indicate the charging state of the energy storage element. the comparator input, fbv cap , is typically connected with a resistor divider from v cap to ground in order to program the final charge voltage. when fbv cap exceeds the rising threshold , the comparator output, v capok , is high impedance. when fbv cap drops below the falling threshold, v capok is pulled to ground. while run = high, capok continues to pull down with reduced strength until both v cap and v sys are below the threshold of the internal pull-down transistor, maximum 1.4v. the comparator operates in both charge and backup mode and is unconditionally released if the ltc3110 is shut down with run = low. chrg operation mode indicator and dir comparator the ltc3110 includes an open-drain dir comparator output pin, chrg, which is typically used to indicate the operation mode of the chip: charge or backup. with the help of a pull-up resistor the output can be used to interface with a microcontroller , or connect to the gate of a p-channel mosfet used as an input isolation switch (see usb application in the typical application section). the dir comparator has hysteresis and the chrg pin is pulled low while v dir is greater than the comparator rising threshold and chrg is released while v dir is lower than its falling threshold. ltc 3110 3110f
17 for more information www.linear.com/ltc3110 the chrg pin is unconditionally released if the ltc3110 is shut down with run = low or in undervoltage condition. note that the dir pin can be driven above v cap or v sys , as long as the voltage is limited to less than the absolute maximum rating. general purpose comparator the ltc3110 includes a voltage comparator with its in - put accessible at the cmpin pin and with a fixed internal reference voltage . the comparator can be used to monitor v cap , v sys or any auxiliary supply voltage . the open-drain output, cmpout, can interface to a microcontroller with the help of a pull-up resistor. the comparator is typically used to supervise v cap and to set a threshold for the lowest v cap voltage toler - ated in backup mode before the system needs to reduce power consumption . the cmpout pin is unconditionally released if the ltc3110 is shut down with run = low or in undervoltage condition (see also the applications information section). shutdown shutdown of the ltc3110 is accomplished by pulling the run pin below 0.3v and ic operation is enabled by pull - ing the run pin above 1.0v. the run pin has an internal pull-down resistor . note that run can be driven above v cap or v sys , as long as the voltage is limited to less than the absolute maximum rating. thermal foldback of charge current to help preventing the ltc3110 from going into ther - mal shutdown when charging very large capacitors , the ltc3110 is equipped with a thermal regulator . if the die temperature exceeds 130 c (typical) the average v sys current limit is lowered to help reduce the amount of power being dissipated in the package. the current limit is reduced to approximately 15% of the programmed limit just before thermal shutdown . the current limit will return to its full value when the die temperature drops below 130c, typically. undervoltage lockout if either voltages at v cap and v sys drop below the under - voltage lockout falling threshold, the ltc3110 will stop operation and the sw1 , sw2, v mid , cmpout, chrg and prog pins will be high impedance. capok will continue to pull down with reduced strength until both v cap and v sys are below the threshold of the internal pull-down transistor, maximum 1.4v. the ltc3110 will resume operation when at least one pin, v cap or v sys , rises above the undervoltage lockout rising threshold. thermal considerations the power switches in the ltc3110 are designed to oper - ate continuously with currents up to the internal current limit thresholds . however, when operating at high current levels there may be significant heat generated within the ic. as a result, careful consideration must be given to the thermal environment of the ic in order to optimize efficiency and ensure that the ltc3110 is able to provide its full-rated output current. specifically, the exposed pad of both the qfn and tssop packages shall be soldered to the pc board and the pc board should be designed to maximize the conduction of heat out of the ic package. if the die temperature exceeds approximately 165c, the ic will enter overtemperature shutdown, all switch - ing will be inhibited and the charge balancer disabled . note: open-drain output pins capok, cmpout and chrg may still pull down while in thermal shutdown. the part will remain disabled until the die cools by approximately 10c. the soft-start circuit is reinitialized in overtemperature shutdown to provide a smooth recovery when the fault condition is removed. o pera t ion + ? v th(cmp) cmpout en cmpin ltc3110 3110 f08 figure 5. general purpose comparator ltc 3110 3110f
18 for more information www.linear.com/ltc3110 the standard ltc3110 application circuit is shown as the typical application on the front page of this data sheet . the appropriate selection of external components is de - pendent upon the required performance of the ic in each particular application given considerations and trade-offs such as pcb area , cost, v sys and v cap voltage , allowable ripple voltage, efficiency and thermal considerations. this section of the data sheet provides some basic guidelines and considerations to aid in the selection of external com - ponents and the design of the application circuit. inductor selection the choice of inductor used in ltc3110 application circuits influences the maximum deliverable backup and charge current, the magnitude of the inductor current ripple, and the power conversion efficiency. the inductor must have low dc series resistance or current capability and efficiency will be compromised. larger inductance values reduce inductor current ripple and will therefore generally yield greater backup current capability. for a fixed dc resistance, a larger value of inductance will yield higher efficiency by reducing the peak current to be closer to the average backup current and therefore minimize resis - tive losses due to high rms currents. however, a larger inductor within any given inductor family will generally have a greater series resistance, thereby counteracting this efficiency advantage . an inductor used in ltc3110 applications should have a saturation current rating that is greater than the worst-case average inductor current plus half the ripple current. the peak-to-peak inductor current ripple for each operational mode can be calculated from the following formula: ? i l(p-p)(buck) = v sys 1.2mhz ? l v cap ? v sys v cap ? ? ? ? ? ? ? i l(p-p)(boost) = v cap 1.2mhz ? l v sys ? v cap v sys ? ? ? ? ? ? l is the inductance in h. in addition to its influence on power conversion efficiency , the inductor dc resistance can also impact the maximum output capability of the buck-boost converter particularly at low v cap voltages. in buck mode, the output current of the buck-boost converter is limited only by the inductor current reaching the current limit threshold. however, in boost mode, especially at large step-up ratios, the v sys backup current capability can also be limited by the total resistive losses in the power stage. these include switch resistances, inductor resistance and pcb trace resistance. use of an inductor with high dc resistance can degrade the v sys backup current capability from that shown in the typical performance characteristics section of this data sheet. as a guideline, in most applications the inductor dc resistance should be significantly smaller than the typical power switch resistance of 60m. the minimum inductor value must guarantee that the worst-case average v cap current plus half the ripple cur - rent doesnt reach the v cap current limit threshold. for the fixed switching frequency of 1.2mhz the recommended typical inductor value is 1.5h. different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. shielded construction is generally preferred as it minimizes the chances of interference with other circuitry . the choice of inductor style depends upon the price, sizing, and emi requirements of a particular application. table 1 provides a small sampling of inductors that are well suited to many ltc3110 applications. table 1. recommended inductors vendor part /style coilcraft www.coilcraft.com xal 50xx series (xal5030-222me_) xal60xx series (xal6030-222me_) epl7040 series (epl7040-222me_) wrth elektronik www.we-online.com we-hci series (744310150, 744314200) we-lhmi series (74437346018, 74437349022) coiltronics www . cooperindustries.com dr73 series (dr73-2r2-r) drq74 series (dr74-2r2-r) vishay www.vishay.com ihlp -2525 series (ihlp-2525ah-01, ihlp-2525cz-01) ihlp-2020 series (ihlp-2020cz-a1) sumida www.sumida.com cdep6d31me series (cdep6d31menp- 2r2mc) murata www.murata.com lqh 66s series (lqh66sn1r5m03) t aiyo yuden www.t-yuden.com nr 6012t2r5ne nr8040t2r0n tdk www.component.tdk.com clf series a pplica t ions i n f or m a t ion ltc 3110 3110f
19 for more information www.linear.com/ltc3110 v sys capacitor selection a low esr capacitor should be utilized at the v sys pin in order to minimize v sys backup voltage ripple. multilayer ceramic capacitors are an excellent option as they have low esr and are available in small footprints. the capacitor value should be chosen large enough to reduce the v sys voltage ripple to acceptable levels. neglecting the capacitor esr and esl, the peak-to-peak v sys voltage ripple can be calculated by the following formulas, where c vsys is the v sys capacitance and i load is the v sys load current. ? v p-p(buck) = v sys 8 ? 1.2mhz ( ) 2 ? l ? c vsys v cap ? v sys v cap ? ? ? ? ? ? ? v p-p(boost) = i load 1.2mhz ? c vsys v sys ? v cap v sys ? ? ? ? ? ? given the v sys current is discontinuous in boost mode, the ripple in this mode will generally be much larger than the magnitude of the ripple in buck mode. in addition to v sys voltage ripple generated across the v sys capacitance, there is also v sys voltage ripple produced across the internal resistance of the v sys capacitor . the esr-generated v sys voltage ripple is proportional to the series resistance of the v sys capacitor. supercapacitor selection and additional bypass the ltc3110 is stable with a total c vcap capacitance value greater than 2mf, or 4mf for each stacked capacitor. su - percapacitors are much larger physically than ceramic or tantalum capacitors , and therefore usually cannot be placed close to the charger . to minimize layout contribution to capacitor esr, the trace width connecting the capacitors to each other and the ic should be as large as possible . the v mid pin trace is not as critical, as it only carries 300ma of average current. it is recommended that a lo - cal decoupling capacitor be placed from v cap to ground , and the capacitor should be placed as close to the ic as possible. multilayer ceramic capacitors are an excellent choice for voltage decoupling as they have extremely low esr and are available in small footprints. while a 10f decoupling capacitor is sufficient for most applications, larger values may be used without limitation. to minimize voltage ripple and ensure proper operation of the ic, a low esr bypass capacitor with a value of 100nf and a second low esr bypass capacitor of 10f should be located as close to the v cap pin as possible . the traces connecting this capacitor to v cap and the ground plane should be made as short as possible. if using a single v sys capacitor where balancing is not required , a capacitor of at least 100nf must be connected between v mid and pgnd. recommended v cap and v sys bypass capacitors the choice of capacitor technology is primarily dictated by a trade-off between cost, size and leakage current. ceramic capacitors are often utilized in switching con - verter applications due to their small size, low esr and low leakage currents . however, many ceramic capacitors designed for power applications experience significant loss in capacitance from their rated value with increased dc bias voltages. for example, it is not uncommon for a small surface mount ceramic capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. as a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a higher voltage rating than required in order to actually realize the intended capacitance at the full operating volt - age. to ensure that the intended capacitance is realized in the application cir cuit , be sure to consult the capacitor vendor s curve of capacitance versus dc bias voltage. the capacitors listed in table 2 provide a sampling of small surface mount ceramic capacitors that are well suited to ltc3110 application circuits. all listed capacitors are either x5r or x7r dielectric in order to ensure that capacitance loss over temperature is minimized. maximum capacitor voltage and balancing the service lifetime of a supercapacitor is determined by its rated voltage, rated temperature, rated lifetime, actual operating voltage, and operating temperature. to extend the life of a supercapacitor the operating voltage and temperature should be reduced from the maximum ratings. the websites for illinois capacitor 1 and maxwell 2 provide the means to determine their capacitor lifetime. a pplica t ions i n f or m a t ion 1 http://www.illinoiscapacitor.com/tech-center/life-calculators.aspx 2 http://www.maxwell.com/products/ultracapacitors/docs/ applicationnote1012839_1.pdf ltc 3110 3110f
20 for more information www.linear.com/ltc3110 using the suggested derated voltage for each capacitor will improve lifetime. the ltc3110 will keep each capacitor voltage at v cap /2 once v cap is higher than typically 2.2v. to prevent an overvoltage on one of the supercapacitors during charging, the v mid voltage is continuously driven from the voltage balancing buffer output with typically 300ma of current capability. the ltc3110 has minimal current draw from v cap at end of charge. care should be taken to limit sources of current that may pull v cap above its programmed regulation value, as there is no way for the ltc3110 to maintain regulation. v sys voltage programming the v sys voltage is set via an external resistor divider connected to the fb pin as shown in figure 6. the resistor divider values determine the v sys backup voltage according to the following formula: v sys = 0.6v ? 1 + r top r bot ? ? ? ? ? ? (1) t he buck-boost converter utilizes voltage mode control and in addition to setting the v sys voltage, the value of r top plays an integral role in the dynamics of the feedback loop . in general, a larger value for r top will increase stability and reduce the speed of the transient response. a smaller value of r top will reduce stability but increase the speed of the transient response . a good starting point is to choose r top = 1m and then calculate the required value of r bot to set the desired v sys voltage according to equation 1. if a large v sys capacitor is used, the bandwidth of the converter is reduced. in such cases r top can be reduced to improve the transient response. if a large inductor or small v sys capacitor is utilized the loop will be less stable and the phase margin can be improved by increasing the value of r top . v cap voltage programming the v cap voltage is set via an external resistor divider connected to the fbv cap pin as shown in figure 7. the resistor divider values determine the maximum v cap voltage according to the following formula: v cap = 1.095v ? 1 + r top r bot ? ? ? ? ? ? care should be taken to limit sources of current that may pull v cap above its programmed maximum value, as there is no way for the ltc3110 to maintain v cap regulation in charger mode (see also figure 15, overvoltage error signal provided to the c). a pplica t ions i n f or m a t ion r bot r top 3110 f09 v sys fb sgnd ltc3110 figure 6. setting the v sys backup voltage v cap v mid 1f 3110 f11 ltc3110 c1 c2 r top r bot v cap fbv cap 1f c1 c2 sgnd 3110 f10 ltc3110 figure 7. v cap voltage programming v mid charge balancer output this pin should be tied to the junction of two series su - percapacitors. a push/ pull buffer output forces the v mid pin to half of the voltage of the v cap pin. generally capaci - tors with equal value of at least 1nf should be connected from v cap to v mid and from v mid to pgnd if the output is unused, e.g., for applications with a single supercapacitor or batteries. figure 8. v mid charge balancer output ltc 3110 3110f
21 for more information www.linear.com/ltc3110 a pplica t ions i n f or m a t ion figure 9. charge balancer unused with single capacitor v cap v mid single capacitor or battery 1f 3110 f12 ltc3110 1nf 1nf figure 10. setting the dir back-up supervisor threshold voltage r top supervised voltage r bot 3110 f13 dir sgnd ltc3110 dir backup supervisor threshold voltage programming the backup supervisor threshold voltage is set via an ex - ternal resistor divider connected to the dir pin as shown in figure 10. the resistor divider values determine the dir super visor threshold voltage according to the following formula: v th(dir _ rising) = 1.095v ? 1 + r top r bot ? ? ? ? ? ? v th(dir _ falling) = 1.045v ? 1 + r top r bot ? ? ? ? ? ? programming backup voltage and dir threshold voltage with improved accuracy in applications with the dir pin voltage and the fb pin voltage divided down from the same v sys voltage, a single resistor divider string is reducing the effect of resistor tolerances and saves one resistor component: figure 11. voltage with reduced tolerances r mid r top backup voltage r bot 3110 f14 v sys fb dir sgnd pgnd ltc3110 c dir r top supervised voltage r bot 3110 f15 dir sgnd pgnd ltc3110 figure 12. filtering dir voltage v th(dir _ rising) = 1.095v ? 1 + r top r bot + r mid ? ? ? ? ? ? v th(dir _ falling) = 1.045v ? 1 + r top r bot + r mid ? ? ? ? ? ? v sys = 0.6v ? 1 + r top + r mid r bot ? ? ? ? ? ? note the direction supervisor threshold v th(dir_rising) must be higher and have enough voltage difference to the backup voltage v sys to accommodate for the resistor tolerances, ripple voltage and voltage dipping from load current steps. if necessary an rc filter in front of the dir pin may reduce the reaction speed of the supervisor , see figure 12. pay attention to the requirement, if the dir input supervises v sys as in figure 11 or in the autonomous applications on page 36, the external v sys supply must be capable to deliver more than the maximum reverse current limit of 2a of the ltc3110, in order to reliably change into charge operation. ltc 3110 3110f
22 for more information www.linear.com/ltc3110 i vsys average current limit programming for charger operation (dir = high) the v sys average current limit is set via an external resis - tor connected between the prog pin and signal ground, sgnd , as shown in figure 13. the resistor value determines the average current into v sys according to the following formula: i vsys = 3k ? r prog for applications with a wide temperature range, the thermal coefficient of resistor r prog must be taken into account. if r prog is > 12.4k, additional r flt and c flt are required for filtering. a pplica t ions i n f or m a t ion if cmpin is driven from a resistor divider or from any output with >200 impdance, connect a 0.1uf capacitor between cmpin and gnd for best performance, see figure 14) . general purpose comparator configuration as redundant v cap supervisor for overvoltage failure detection component failures interrupting the v cap voltage feedback (fbv cap ) can potentially cause an over voltage condition at v cap during charging. the general purpose comparator can be configured as the supervisor providing an overvolt - age error signal to the microcontroller (see figure 15). r prog r f lt 6.04k (opt) c f lt 10nf (opt) 3110 f16 prog sgnd ltc3110 figure 13. setting the v sys average current limit figure 15. overvoltage error signal provided to the c cmpin configuration as general purpose voltage supervisor with hysteresis the resistor divider values, see figure 14, determine rising and falling threshold v th according to the following formula: v th(rising) = 0.65v ? 1 + r top r bot ? ? ? ? ? ? v th(falling) = 0.59v ? 1 + r top r bot ? ? ? ? ? ? v dd r top r bot v th 3110 f17 cmpin cmpout out ltc3110 c cmpin 0.1f figure 14. general purpose voltage supervisor ltc3110 v dd 3110 f18 c cmpout run cmpin v cap r top c1 c2 r bot 10k err c cmpin 0.1f sv sys filtering in many noise critical applications it is useful to filter the signal supply pin, sv sys , with a small rc filter on the pcb, see figure 16. note, if the filter is added any further loads connected to the sv sys pin must be checked if they are small with respect to the resistor impedance and not creating undesired voltage drops at sv sys . run, dir, mode, cmpin inputs digitally controlled the run, dir, mode and cmpin comparator inputs can be driven digitally from an external microcontroller. 3110 f19 sgnd sv sys c sys v sys r svsys 51.1 c svsys 220nf ltc3110 figure 16. sv sys filtering ltc 3110 3110f
23 for more information www.linear.com/ltc3110 a pplica t ions i n f or m a t ion open-collector outputs chrg, capok and cmpout open-collector outputs can be connected together with other external signals in wired or configuration and pull-up resistors for level shifting when interfacing into c inputs. ltc3110 c 3110 f20 cmpin sgnd mode dir run figure 17. inputs run, dir, mode, cmpin driven from a microcontroller ltc3110 c v dd 3110 f21 sgnd cmpout capok chrg figure 18. outputs chrg, capok, cmpout interfacing to c table 2: recommended supercapacitors and ultracapacitors vendor value (f) esr (m) volt age (v) temperature range (c) size (mm) w l h murata electronics dmf3r5r5l334m3dta0 dmf3z5r5h474m3dta0 0.33 0.47 60 40 4.2 (5.5 peak) 4.2 (5.5 peak) C30 to 70 C30 to 70 14.0 21.0 2.5 14.0 21.0 3.2 t ecate tpl-10/10x30f tpl-25/16x26f tpl-100/22x45f tple-25/16x26f tple-100/22x45f tpls-400/35x60f 10 25 100 25 100 400 85 42 15 42 15 12 2.7 2.7 2.7 2.3 2.3 2.7 C40 to 65 C40 to 65 C40 to 65 C40 to 85 C40 to 85 C40 to 65 10.0 10.0 30.0 16.0 16.0 26.0 22.0 22.0 45.0 16.0 16.0 26.0 22.0 22.0 45.0 35.0 35.0 60.0 av x bz015a503z_b bz015a104z_b 0.05 0.1 160 80 5.5 5.5 C20 to 70 C20 to 70 28.0 17.0 4.1 28.0 17.0 6.7 cap -xx hs206f hs230 0.6 1.2 70 50 5.5 5.5 C40 to 85 C40 to 85 39.0 17.0 2.5 39.0 17.0 3.8 cooper bussmann a1635-2r5475-r m1325-2r5905-r hb1625-2r5256-r hv1860-2r7107-r 4.7 9 25 100 25 20 36 10 2.5 2.5 2.5 2.7 C25 to 70 C40 to 60 C25 to 70 C40 to 65 16.0 16.0 35.0 13.0 13.0 26.0 16.0 16.0 25.0 18.0 18.0 60.0 illinois capacitor 506der2r5slz 357der2r5sez 50 100 30 12 2.5 2.5 C40 to 70 C40 to 70 18.0 18.0 60.0 35.0 35.0 60.0 maxwell bcap0005 bcap0100t01 5 100 170 15 2.7 2.7 C40 to 65 C40 to 65 10.0 10.0 20.0 22.0 22.0 45.0 t aiyo y uden pas2026fr2r5504 pas0815ls2r5105 lic2540r3r8207 0.5 1 200 55 70 50 2.5 2.5 2.2 to 3.8 C25 to 60 C25 to 70 C25 to 70 26.0 20.0 0.9 8.0 8.0 15.0 25.0 25.0 40.0 the open-collector outputs can also be used to drive small loads up to 20ma, e.g., miniature lamps or leds. ltc 3110 3110f
24 for more information www.linear.com/ltc3110 pcb layout considerations the ltc3110 switches large currents at high frequencies. special care should be given to the pcb layout to ensure stable, noise-free operation. figures 19 and 20 depict the recommended pcb layout to be utilized for the ltc3110, if a 2-layer pcb is being used. a 4-layer pcb layout is recommended for thermal and noise reasons . a few key guidelines follow: 1. all circulating high current paths should be kept as s hort as possible . this can be accomplished keeping the routes to the components in figures 19 and 20 as short and as wide as possible. capacitor ground connections should be connect by vias down to the ground plane in the shortest route possible . the bypass capacitors c sys and c cap should be placed as close to the ic as possible and should have the shortest possible path to ground. 2. the components shown and their connections should all be placed over a complete ground plane. 3. use of vias in the die attach pad will enhance the ther - mal environment of the charger, especially if the vias extend to a ground plane region on the exposed bottom surface of the pcb. 4. keep the connections to the fb, prog, dir, cmpin and fbv cap pins as short as possible and away from the switch pin connections. a pplica t ions i n f or m a t ion table 3. representative bypass and v sys capacitors part number value (f) voltage (v) footprint avx 12066d106k 12066d226k 12066d476k 10 22 47 6.3 6.3 6.3 0603 0805 0805 kemet c0603c106m9pactu c0805c226m9pactu c0805c476m9pactu 10 22 47 6.3 6.3 6.3 0603 0805 0805 murata grm188d70j106ma73 grm219b30j226me47 grm21bb30j476me15 10 22 47 6.3 6.3 6.3 0603 0805 0805 tdk c1608x7s0j106m080ac c2012x5r0j226m085ab c2012x5r0j476m125ac 10 22 47 6.3 6.3 6.3 0603 0805 0805 t aiyo y uden jmk107bj106ma jmk212abj226md jmk212bbj476mg 10 22 47 6.3 6.3 6.3 0603 0805 0805 ltc 3110 3110f
25 for more information www.linear.com/ltc3110 a pplica t ions i n f or m a t ion 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 17 16 15 14 13 19 18 21 20 c2 bottom copper layer c1 c sys 3110 f22 via to ground plane l1 c cap component names: see typical application on page 27 ltc3110 top layer figure 19. pcb component placement of the tssop package ltc 3110 3110f
26 for more information www.linear.com/ltc3110 a pplica t ions i n f or m a t ion 1 2 3 4 5 6 18 7 7 7 10 11 12 24 23 22 21 20 19 c2 bottom copper layer c1 l1 c cap 17 16 15 14 13 c sys via to ground plane 3110 f23 component names: see typical application on page 27 ltc3110 top layer figure 20. pcb component placement of the qfn package ltc 3110 3110f
27 for more information www.linear.com/ltc3110 typical a pplica t ions 3.3v/2a output from stack of supercapacitors backup/recharge application with active voltage balancing l1 1.5h sw2 ltc3110 sv sys v sys c sys 47f c svsys 220nf v sys 3.25v 2a c cap 1f c1 10f c2 10f r1 1910k r2 523k r3 1910k r4 523k r prog 6.04k r svsys 51.1 r5 976k r6 221k 3110 ta02 sw1v cap fbv cap cmpin mode run pgnd v mid r sen prog fb chrg capok cmpout dir capok caplow at v cap = 2.8v dir 1000k 1000k c 12v bus supervisor sgnd 12v bus main step-down dc/dc fb c cmpin 0.1f ltc 3110 3110f
28 for more information www.linear.com/ltc3110 t ypical a pplica t ions 1.8v/300ma output from single capacitor discharged from 2.5v to 1v and with reserve available down to 0.3v capok caplow dir 1000k 1000k c 12v bus supervisor ltc3110 c sys 47f v sys 1.83v 300ma c cap 1f c mid2 1nf c mid1 1nf c1 10f r1 2000k r2 1580k r3 1300k r4 1870k r prog 6.04k r5 976k r6 475k 3110 ta03 v cap fbv cap cmpin mode run pgnd v mid rsen prog fb chrg capok cmpout dir sgnd l1 1.5h sw2 sv sys v sys c svsys 220nf r svsys 51.1 sw1 12v bus main step-down dc/dc fb c cmpin 0.1f ltc 3110 3110f
29 for more information www.linear.com/ltc3110 typical a pplica t ions 500ma usb charge/backup application with variable charging power, p chrg , depending on system load l1 1.5h sw2 ltc3110 sv sys v sys c sys 330f c fb 10pf c dir 1nf c cap 1f p chrg = p usb ? p sys usb m1 irlml6402 c1 10f c2 10f r1 1910k r off 3.3k r2 511k r7 7.50k r8 2.49k r prog 6.04k r6 133k r5 976k 1000k 3110 ta04 1000k 1.2v, 1a usb data 1.8v, 0.2a 2.5v, 0.1a 5v, 0.1a 5v c end of chrg caplow sw1v cap fbv cap cmpin mode run pgnd v mid r sen p sys prog fb chrg capok cmpout dir sgnd system dc/dc regulators c svsys 220nf r svsys 51.1 r3 1910k r4 1270k p usb up to 5v ? 500ma c cmpin 0.1f 1v/div 100s/div 3110 ta04b i li 2a/div chrg 5v/div v usb v sys backup charging 1v/div 100s/div 3110 ta04c i li 2a/div chrg 5v/div v usb v sys backup charging disconnect usb connect transition usb disconnect transition ltc 3110 3110f
30 for more information www.linear.com/ltc3110 typical a pplica t ions autonomous backup and recharge application with input isolation switch l1 2.2h sw2 ltc3110 sv sys v sys c sys 150f c main 47f back-up 3.2v c cap 1f c1 100f c2 100f r1 1910k r2 536k r4 681k r3 1910k r prog 3.01k r6 215k r5 931k r8 4.53k r7 9.31k r off 3.3k r svsys 51.1 m1 irlml6402 1.5a v main charging 3.6v 4% 1000k 1000k 3110 ta08 capok caplow 1.2v chrg 1.8v 2.5v 3.6v/3.21v sw1v cap fbv cap cmpin mode run pgnd v mid r sen prog fb chrg capok cmpout dir sgnd system dc/dc regulators main step-down dc/dc fb 12v bus c svsys 220nf c cmpin 0.1f il 1a/div 1v/div chrgb 2v/div 500s/div charge sleep backup 3110 ta06b 0a v main v sys 0v 0v ltc 3110 3110f
31 for more information www.linear.com/ltc3110 typical a pplica t ions lead acid battery backup/recharge application l1 1.5h sw2 ltc3110 sv sys v sys c sys 150f c cap 1f 47f c mid1 1nf c mid2 1nf 12v m1 irlml6402 3.6v r1 976k r off 10k r2 316k r7 9.31k r8 4.53k r prog 6.04k r6 226k r5 976k 1000k 3110 ta05 1000k 1.2v 1.8v 2.5v 3.21v/ 3.6v end of chrg battlow sw1v cap fbv cap cmpin mode run pgnd v mid r sen prog fb chrg capok cmpout dir sgnd system dc/dc regulators r3 1910k batt 4v 2.5ah r4 604k + 3.3v ldo or buck regulator c cmpin 0.1f ltc 3110 3110f
32 for more information www.linear.com/ltc3110 typical a pplica t ions nimh battery backup/recharge application ltc3110 c sys 47f v sys 3.25v 2a c mid2 1nf c mid1 1nf c cap 1f r3 1910k nimh 1.2v 3700mah 3 r4 604k r prog 12.4k r fast 8.06k r5 976k r6 221k 1000k 3110 ta06 v cap fbv cap cmpin mode run pgnd v mid r sen prog fb chrg capok cmpout dir sgnd + c l1 1.5h sw2 sv sys v sys c svsys 220nf r svsys 51.1 sw1 dir run fastchrg fbvcap adin rtemp battlow v cc v sys supervisor note on digital control signals in nimh backup/recharge application: charging is initiated by pulling dir = high and fbvcap = low. charging is terminated by pulling dir = high and fbvcap = high (fbvcap must be 1.2v). system back-up is initiated by forcing fbvcap = low, waiting 5s, then forcing dir = low. general safety note: charging must be terminated if the battery voltage or charge time have reached their maximum values or if the battery temperature is above or below the save operating region of the battery, see datasheet of the battery. the thermistor, used for measuring the temperature, must have good thermal connection to the battery pack. c cmpin 0.1f ltc 3110 3110f
33 for more information www.linear.com/ltc3110 24h/7d active solar powered sensor/transmitter supply charging states charging with solar current and 24/7 backup l1 2.2h sw2 ltc3110 sv sys v sys c sys1 47f c sys2 4700f <30m c sys3 4700f <30m c cap 47f v solar i solar q1 pbss302 d1 schottky optional c1 100f c2 100f r1 1910k r11 348 r2 511k r prog 3.01k r6 221k r7 953k r8 422k r9 1000k r5 976k 3110 ta09 transmitter gsm display sensor micro controller end of charge caplow high backup power mode sw1v cap fbv cap cmpin mode run pgnd v mid r sen prog fb chrg capok cmpout dir sgnd r10 1000k c svsys 220nf r svsys 51.1 r3 1910k r4 523k s0 s1 s2 pfo rst gnd v cc ltc2935-2 2a pulse v sys = 3.25v low ripple high backup power mode, mode = high 3.42v/3.58v solar charging, mode = low d1 solar cell module 6v, 150ma ~12 cells primary battery lith 3v, 1ah optional supercaps m1 2n7002 m2 2n7002 + ? i sys c cmpin 0.1f typical a pplica t ions i vcap 1a/div 0a v solar 5v/div 0v i solar 100ma/div 0a v sys ac coupled 100mv/div 5ms/div 3110 ta09c charging v cap = 4v pre charging c harging with solar current and 24/7 backup : if daylight is present , the supercapacitors are charged up with the output current of the solar cells . when daylight is not present , the supercaps partially discharge and provide the backup power to maintain v sys . high backup power mode ( no waveform ): if mode = high and with the supercapacitors charged , the application can provide the v sys backup voltage with low ripple and full output current capabilities . mode = high stops further charging . c ha rging s tat es : if mode = low : the v sys voltage is fed with current from the solar module or is regulated from the ltc 3110 in burst mode if sunlight is missing . if sunlight is present , v sys is regulated with a two point voltage regulation defined by dir rising and dir falling thresholds . the application has three states of operation : 1. c sys pre-charging state : the solar panel output current pre-charges the capacitor c sys until the dir voltage rises above the dir rising threshold and the supercapacitor charging state is entered . 2. sup ercapacitor charging state : the ltc 3110 charges the supercapacitors by drawing current from capacitor c sys until the v sys voltage falls below the dir falling threshold and the v sys pre-charging state is re-entered . the lt c 3110 to ggles b etween the pre-charging state and the charging state until fbv cap is above the fbv cap rising threshold and the charge sleep state is entered . 3. ch arge sleep state ( no waveform ): v cap is fully charged and fbv cap is above the fbv cap falling threshold while the v sys voltage is regulated with ltc 3110s burst mode backup operation . in the charge sleep state , the solar module is isolated from v sys . startup with discharged supercaps : the v sys voltage is monitored with the ltc 2935 -2 supervisor enabling the ltc 3110 only at a voltage above 2.7 v. if powered from high impedance sources ( e . g . solar cells ). v sys must be initially high enough to skip the soft start function of the ltc 3110, see soft start ( backup mode ) in the operation section . notes : the required panel size and the number of solar cells in series or in parallel strongly depends on the local sunlight conditions . v solar must be one v be higher than v sys (3.58 v + 0.7 v = 4.3 v) in the lowest light condition to deliver solar current . to prevent overvoltaging of v sys , the i vsys average current limit must be at least four times larger than the maximum solar current ( i vsys _ prog > 4 i solar _ max ). alternatively , output chrg can be additionally connected to the base of q1 to isolate the solar panel during charging . the absolute maximum of v solar is defined from the v ceo value of q 1 ( e.g . 20 v) which allows the connection of modules with open circuit voltages of v oc > 5.25 v. optionally a primary battery can be added as reserve to cover poor light conditions . example solar module manufacturers : sharp , panasonic , powerfilm 2v/div v sys 2v/div i solar 20ma/div 3110 ta09b ltc 3110 3110f mode = low i sys = 0.5ma day 1 day 2 day 3 day 4 8h/div v cap
34 for more information www.linear.com/ltc3110 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe24 (aa) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 7.70 ? 7.90* (.303 ? .311) 3.25 (.128) 2.74 (.108) 2021222324 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.25 (.128) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1771 rev b) exposed pad variation aa ltc 3110 3110f
35 for more information www.linear.com/ltc3110 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) ltc 3110 3110f
36 for more information www.linear.com/ltc3110 ? linear technology corporation 2015 lt 0615 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3110 r ela t e d p ar t s typical a pplica t ion autonomous backup and recharge application (3.6v nominal, 3.2v backup voltage) ltc3110 c sys 47f 3.6v 4%, 2a nominal from main dc/dc 3.21v, 1.5a backup c cap 1f c1 10f c2 10f r1 1910k r2 681k r3 1910k r4 715k r prog 6.04k r6 200k 1000k 1000k 1000k r5 1020k r7 280k 3110 ta07 v cap fbv cap cmpin mode run pgnd v mid r sen prog fb chrg capok cmpout dir sgnd 1.2v chrg capok caplow 1.8v 2.5v 3.6v/3.21v system dc/dc regulators l1 2.2h sw2 sv sys v sys c svsys 220nf r svsys 51.1 sw1 12v bus main step-down dc/dc 2a + i sys = minimum requirement fb note: the driving capability of the main dc/dc should exceed the maximum reverse current limit of the ltc3110 plus i sys ,the load current demanded from the system dc/dc regulators connected at v sys . c cmpin 0.1f part number description comments ltc3225/ltc3225-1 150ma supercapacitor charger low noise, constant frequency charging of tw o series supercapacitors, automatic cell balancing prevents capacitor overvoltage during charging, 2mm 3 mm dfn-10 package ltc3226 2-cell supercapacitor charger with backup powerpath ? controller 1/2 multimode charge pump supercapacitor charger with automatic cell balancing. internal 2a ldo backup supply (cpo to v out ). automatic main/backup switchover, 3mm 3mm qfn-16 package ltc3625/ltc3625-1 1a high efficiency 2-cell supercapacitor charger with automatic cell balancing high efficiency step-up/step-down charging of tw o series supercapacitors, automatic cell balancing. programmable charging current up to 500ma (single inductor), 1a (dual inductor), 3mm 4mm dfn-12 package ltc3128 3a monolithic buck-boost supercapacitor charger and balancer with accurate input current limit 2% accurate average input current limit programmable to 3 a , active charge balancing, charges 1 or 2 capacitors, v in range: 1.73 v to 5.5v , v out range: 1.8 v to 5.5v , 20-lead (4mm 5 mm 0.75 mm) qfn and 24-lead tssop packages ltc3350 high current supercapacitor backup controller and system monitor synchronous step-down cc/cv charging up to four series supercapacitors v in : 4,5v to 35v, 14-bit adc for monitoring system voltages/currents, capacitance and esr, internal active balancers, 38-lead 5mm 7mm qfn package ltc 4425 linear supercap charger with current- limited ideal diode and v/i monitor constant-current/constant-voltage linear charger for 2-cell series supercapacitor stack, 2a charge current, auto cell balancing, 20a quiescent current, 3mm 3mm dfn-12 and a msop-12 packages ltc3127 1a buck-boost dc/dc converter with programmable input current limit programmable (0.2a to 1a) 4% accurate average input current limit, 1.8v to 5.5v (input) and 1.8v to 5.25v (output) voltage range, 3mm 3mm 0.75mm dfn-10 and msop-12 packages ltc 3125 1.2 a i out , 1.6 mhz, synchronous boost dc/ dc converter with adjustable input current limit 94% efficiency, v in : 1.8v to 5.5v, v out(max) = 5.25v, i q = 15a, i sd < 1a, 2mm 3mm dfn-8 package ltc3441/ltc3441-2/ ltc3441-3 1.2a i out , 2mhz, synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.4v to 5.5v, v out : 2.4v to 5.25v, i q = 50a, i sd < 1a, 3mm 4mm dfn-12 package ltc3113 3a low noise buck-boost dc/dc converter 96% efficiency, v in : 1.8v to 5.5v, v out : 1.8v to 5.5v, i q = 40a, i sd < 1a, 4mm 5mm dfn-16 and 20-lead tssop packages ltc3538 800ma i out , 1 mhz, synchronous buck- boost dc/dc converter 95% efficiency, v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 35a, i sd < 1a, 2mm 3mm dfn-8 package ltc3536 1a i out , 300khz, synchronous buck-boost dc/dc converter 95% efficiency, v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 32a, i sd < 1a, 3mm 3mm dfn-10 and msop-12 packages ltc 3110 3110f

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